Synapse Design Interview Questions
& Process

I applied through LinkedIn and a recruiter from HR called me the next day to set up an interview. There were two rounds in total. The first round was a video call on Teams where the interviewer asked me about myself and my projects. Then, she asked questions about UVM and SV, and also gave me some code to determine the output. The second round, also a 30-minute video call on Teams, focused on my previous projects and included some logical questions based on them.

on the challendges in tile level What is cluster based design? Describe about cluster based region? 2. What are the problems are faced when placing long net of FF to FF path and Short net of FF to FF path? 3. Is timing driven placement advantageous over the functionality based placement? Explain briefly. 4. Explain In Place Optimization and Timing Delay? 5. How to do Congestion optimization and balance slew? on good drc fixing on good timing fix on ir fixing on the relevant nm technology expertise

The interview process included a written test with two sections: MCQs covering basics of CMOS, Digital Design, and C programming, and descriptive questions asking to write programs like palindrome and pattern generation, along with Digital Electronics questions. This was followed by a telephonic technical interview focusing on basic CMOS concepts, characteristics, setup and hold times, gates, the difference between combinational and sequential logic, and Verilog basics. The third round was a telephonic technical and HR interview, covering STA basics, VLSI basics, and a discussion about projects, with the HR part being easy.

So first there was like a written test, topics covered CMOS Fundamentals, Logic Design, Protocol, Timing and C programming. It was split into parts. Part 1: CMOS Fundamentals asked about SRAM/DRAM cells, stick diagrams, inverters, enhancement vs depletion transistors, CMOS advantages and power consumption, and latch-up. Part 2: Logic Design covered half/full adders with K-maps, D-flip flops/latches, counters, detecting 1s in a pattern, combinational vs sequential circuits, Mealy vs Moore FSMs, converting gates, and metastability. Part 3: Protocol involved the OSI model and DAC/ADC. Part 4: Timing was about D flip flop timing parameters. Part 5: C programming (logical) had a question on bitwise operators and a preprocessor directive. Part 6: C programming (pointers) had questions on typedef and malloc. Part 7: C programming (General) asked about swapping variables without a temp, division remainder, array passing, and fgets vs gets. There was also an objective part with 25 questions which was easy.