Xilinx Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 33 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Xilinx.
Xilinx
Design Engineer
Mid Easy Positive experience Accept offer 5 rounds
Interview process
Recruiter call Phone screen Onsite
Interview formats
Technical Coding Behavioral
The interview process started with a 30-minute telephonic interview covering digital design basics, Verilog, and timing. This was followed by a full day of on-site interviews, which included 4 technical interviews and an HR chat. Topics to focus on include Digital design concepts (Muxes, FFs, Timing Params, Synchronizers, Asyn FIFOs, Clock Domain Crossings), Verilog coding fundamentals (Case, if-else, practical design problems), SystemVerilog basics (Tasks, Processes, Fork Join), Computer Architecture (Pipelining, Load-store Arch), and scripting languages (Python/Perl/Tcl).
Confirmed questions5 questions
- Telephonic Round: Had simple digital, Verilog, and timing questions (30 mins).
- Onsite Interview: Round 1 (45 mins): Asked about simple digital questions, Verilog code (difference between Case and if-else, Blocking-Nonblocking differences, unintentional latch problem), power reduction techniques (Clock Gating), and follow-up questions on these topics, plus questions about my previous work and the overall function of a module I discussed.
- Onsite Interview: Round 2 (45 mins): Focused on verification basics like What is fork-Join?, Tasks and functions, Pass by value, Pass by Reference, and the logic behind linked list entry removal (how the address pointer changes).
Xilinx
Design Engineer
Entry Average Neutral experience Accept offer 4 rounds
Interview process
Recruiter call Phone screen Technical screen
Interview formats
Technical Coding Behavioral
Got my resume through a referral from a senior who works there, they reached out after three months. The first step was a telephonic round with basic questions on digital design, flip flops, latches, mux, and Python. The following week, three more telephonic interviews were scheduled. These focused on my resume projects, Verilog, Python, digital design concepts, static timing analysis, Mealy Moore FSM, and a traffic light controller FSM. The questions were generally easy. Four days later, they let me know the results.
Confirmed questions1 question
- Could you explain the difference between a tuple and a list?
Xilinx
CAD Engineer
Entry Easy Positive experience Accept offer 1 round
Interview process
Recruiter call Technical screen Onsite
Interview formats
Coding Technical
I was interviewed on campus at IIT Kharagpur when Xilinx came for campus fair. I was asked about basic VHDL code for ring counter, couple of C++ questions and also tested some scripting knowledge. I attended for CAD Engineer profile and I thought it would more software oriented but then I was asked to code ring counter in VHDL which surprised me. Later in the job role I understood that CAD Engineer should also have good understanding in Electronics if not expert like
Confirmed questions3 questions
- Could you write some basic VHDL code for a ring counter?
- Do you have any experience with C++?
- Can you tell me about your scripting knowledge?
Xilinx Engineer Interview Questions
Quoted word for word from Xilinx interview reports.
“Write a function to detect a one-hot encoded state variable.”
Read reports →“Could you explain the difference between a tuple and a list?”
Read reports →“Could you write some basic VHDL code for a ring counter?”
Read reports →“Could you explain Moore and Mealy state machines?”
Read reports →“Regarding a provided Verilog code snippet, can you explain the synthesis outcome of its different constructs?”
Read report →“Can you describe all the components of a microcontroller board?”
Read report →“What are the different techniques for power reduction that can be applied post-placement?”
Read report →“Can you analyze this circuit and determine the output?”
Read report →“Can you explain Setup and Hold calculations using waveforms?”
Read report →Formats, difficulty and experience
Across all 33 Xilinx interview reports.