Samsung R&D Institute India - Bangalore Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 7 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Samsung R&D Institute India - Bangalore.
Samsung R&D Institute India - Bangalore
Physical Design Engineer
Entry Average Positive experience Accept offer 2 rounds
Interview process
Take home Phone screen
Interview formats
Technical Coding
First, there was a written test with 48 questions covering digital and analog electronics, Verilog, and basic VLSI topics. It lasted 2 hours. Key digital topics included ADC, DAC, and counters. Key analog topics included Op-Amp and PLL. No aptitude questions or sectional cutoffs were present. After passing the written test (you'll know within a week), there's a Skype interview.
Confirmed questions5 questions
- Tell me about your projects or internships.
- Can you discuss low power techniques?
- What is your understanding of STA?
Samsung R&D Institute India - Bangalore
ASIC Engineer
Senior Average Positive experience No offer 2 rounds
Interview process
Recruiter call Technical screen
Interview formats
Behavioral Technical
The interview process started with a discussion about my previous job experience and some related questions. They asked about frequency division to create a 256kb memory from 32kb ones, a question on FSM, and what a reset synchronizer and RDC problems are.
Confirmed questions5 questions
- Can you tell me about your experience in your previous job?
- Regarding frequency division, how would you create a 256kb single port memory from 32kb memories by dividing by 3?
- Could you elaborate on a question related to Finite State Machines (FSM)?
Samsung R&D Institute India - Bangalore
Physical Design Engineer
Mid Average Positive experience No offer 3 rounds
Interview process
Recruiter call Technical screen Onsite
Interview formats
Technical Coding
It was pretty good, the interviewers were helpful and gave hints towards the solution. The questions were mainly about STA and PNR, with some scenarios involving flop placement and optimization in VLSI.
Confirmed questions4 questions
- Can you tell me about your overall experience and the projects you've completed?
- Could you walk me through the PNR flow in detail and any challenges you've encountered at your current company?
- Let's talk about multicorner STA and power optimization.
Samsung R&D Institute India - Bangalore Silicon / Chip Design Engineer Interview Questions
Quoted word for word from Samsung R&D Institute India - Bangalore interview reports.
“What is a reset synchronizer?”
Read reports →“Regarding frequency division, how would you create a 256kb single port memory from 32kb memories by dividing by 3?”
Read reports →“What can you tell me about CMOS latch up?”
Read reports →“How do you fix setup and hold violations in a design?”
Read reports →“Could you explain blocking vs. non-blocking assignments?”
Read report →“How is an Eco implemented during the signoff stage?”
Read report →“What are RDC problems?”
Read report →“Can you describe your understanding of resets in digital design?”
Read report →“Can you solve these two puzzles?”
Read report →Formats, difficulty and experience
Across all 7 Samsung R&D Institute India - Bangalore interview reports.