Cyient Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 8 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Cyient.
Cyient
Physical Design Engineer
Senior Average Positive experience No offer 2 rounds
Interview process
Take home Technical screen
Interview formats
Technical Coding
Once your resume is shortlisted, they will email you about the written interview process and the topics that might be covered. The exam date and time will be given, and you'll get the test link right before it starts.
Confirmed questions1 question
- How many 2:1 multiplexers are needed to construct a 32:1 multiplexer?
Cyient
Physical Design Engineer
Entry Average Positive experience Accept offer 3 rounds
Interview process
Technical screen Technical screen Background check
Interview formats
Technical Technical Behavioral
The interview process had two main steps: first, a technical and/or aptitude test, and then an interview for those who passed. The test had two parts: aptitude and electronics. The aptitude questions were pretty standard, nothing too tough. Same for the electronics questions, which covered digital electronics and VLSI. They scheduled the interview about 2-3 weeks after the test. The main interview lasted 30-45 minutes and was manageable if you knew the material well. After that, there was a short 10-minute HR round.
Confirmed questions1 question
- Could you define signal integrity and explain how it's assessed? Also, what measures can be taken to mitigate the impacts of noise and cross-talk?
Cyient
Digital Design Engineer
Mid Average Positive experience No offer 2 rounds
Interview process
Phone screen Technical screen
Interview formats
Technical Coding
The interview process involved either an online test or a phone screening. The focus was on digital design basics (MUX, FSM, timing), Verilog/SystemVerilog syntax, and testbenches with assertions. Sometimes, aptitude or C programming was also tested. They looked for knowledge of SystemVerilog features like always_comb, interface, modport, virtual, constraint, and randc. Understanding of UVM architecture (agent, driver, monitor, sequencer, scoreboard), functional coverage, SVA, and constrained-random testing was important. Debugging waveform issues was also part of it.
Confirmed questions1 question
- Can you explain how to develop a behavioral model in Verilog?
Cyient Silicon / Chip Design Engineer Interview Questions
Quoted word for word from Cyient interview reports.
“How many 2:1 multiplexers are needed to construct a 32:1 multiplexer?”
Read reports →“Can you explain the noise margin in CMOS?”
Read reports →“What are the different regions of operation in CMOS?”
Read reports →“Could you define signal integrity and explain how it's assessed? Also, what measures can be taken to mitigate the impacts of noise and cross-talk?”
Read reports →“What are the designing softwares Tool flow?”
Read report →“What about the basics of STA hold timing?”
Read report →“Can you explain some Verilog snippet questions?”
Read report →“Could you explain setup and hold analysis?”
Read report →“How to rectify the bugs?”
Read report →Formats, difficulty and experience
Across all 8 Cyient interview reports.