Synopsys Silicon / Chip Design Engineer Interview Questions
& Process

It was a two round interview. The first round focused on testing my C++ and CMOS knowledge. For C++, I was asked about class and object concepts, the difference between reference and pointer, and to provide a ternary expression example. On the CMOS side, I had to describe its circuit principles, explain its complementary nature, and discuss power reduction. The second round was a managerial interview, focusing on experience and problem-solving. I was asked to share a challenge and my approach, describe a successful team collaboration, and how I handle tight deadlines. This round also covered teamwork and communication, with questions about examples of effective collaboration and conflict resolution. Finally, it touched on adaptability and learning, asking for a quick learning experience and how I stay updated with new skills.

The interview process included 3 rounds, with about 90% of each being technical. I met with two engineers from the Security IP team and my potential manager. The first interview was with my future boss, where we discussed the team's operations, current projects, my potential role, and my background and goals. This then transitioned into technical questions about general ASIC Design concepts like power, synthesis, design flow, and CDC. The subsequent two interviews were entirely technical, focusing on specific Digital Design modules and architectures such as FIFOs, memories, datapath, and basic Cybersecurity protocols.

So, there were 5 rounds in total. It kicked off with the hiring manager, who was super nice. He introduced himself, then went into the nitty-gritty of the role and what I could expect day-to-day. Round two was with a junior engineer, and it went great, mostly entry-level stuff. She was well-prepared and covered pretty much all the technical bases. The third round was with the director, a really sweet person. No technical questions at all, just a casual chat, which is what I figured for a director. He also elaborated on the role and his expectations for me. Then, round four was with a senior architect who, apparently, knows everything about FPGAs. He asked me to discuss the breadth and depth of FPGA knowledge, and threw in some specific questions about architecture and timing constraints. Overall, that round felt positive. The fifth and final round was with a senior manager leading the verification team in India. To start, he showed up 30 minutes late, didn't introduce himself, and didn't turn on his camera even though mine was on. He then asked me to design a circuit to detect a 1ns asynchronous pulse. I suggested a transparent latch, but he shot it down, saying FPGAs don't have transparent latches, which left me stumped. He then fumbled with timing constraint questions, but I managed to grasp what he was getting at. After I answered, he rudely told me I should have said that from the start. When I asked if I had any questions, I inquired about his role and how the Bangalore verification team interacts with the Sunnyvale FPGA design/emulation teams. His response was a dismissive 'You don't need to know that,' followed by him abruptly ending the call. This 5th round really highlighted a toxic work culture in the India office. The interviewers from Sunnyvale were professional and pleasant, but the individual from Bangalore was truly awful, borderline abusive. It took me about a week to process the whole experience. I never expected such unprofessional conduct from a company like Synopsys. My advice to the hiring team is that Synopsys really needs to train its hiring teams on how to treat candidates.