SanDisk Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 14 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at SanDisk.
SanDisk
ASIC Design Engineer
Intern Average Negative experience No offer 2 rounds
Interview process
Recruiter call Phone screen Technical screen Onsite
Interview formats
Technical Coding Behavioral
I had two phone calls. The first one was about my projects with Xilinx FPGA, setup time, hold time, and how asynchronous reset signals are asserted and deasserted. They also asked for Verilog code for a flipflop and C code for sorting. It was about 30 minutes. The second call was with the manager. He asked about my Xilinx FPGA projects and how I did P&R. I told him we didn't do anything and that Xilinx does it automatically, which he seemed disappointed about. Then he asked about PrimeTime, which I don't have much experience with, leading to more disappointment. He also asked if I knew regular expressions, which I don't, so he was disappointed again. This call was only 20 minutes.
Confirmed questions2 questions
- Could you explain the assertion and deassertion of an asynchronous reset signal and its system impact?
- What are the effects of asynchronous reset signal assertion and deassertion on the system?
SanDisk
FPGA Engineer
Mid Easy Positive experience No offer 1 round
Interview process
Recruiter call Technical screen Onsite
Interview formats
Technical Behavioral
I arrived and checked in, got a visitor badge. My interviewer met me and we went to the interview room. They offered me a drink from the kitchenette, I chose water. After settling in, we had a brief friendly chat, mentioning some mutual contacts. The interviewer then explained the job's requirements and the different aspects of the role. I shared my work experience, and then they asked if I was comfortable tackling a technical problem. I solved it, and they seemed pleased. They asked if I had any questions, and we wrapped up on a positive note.
Confirmed questions1 question
- Could you design a component that takes a 1-bit input with a pulse width of one clock cycle on `clk_in`, and outputs data on `clk_out` (which is faster/smaller)? The output should only be a single clock pulse on `clk_out`. What are the constraints on the rate for this component, considering only standard FPGA building blocks?
SanDisk
ASIC Design Engineer
Entry Average Positive experience Decline offer 2 rounds
Interview process
Recruiter call Onsite
Interview formats
Technical Coding Behavioral
Met a hiring manager at a college career fair, and then got called on site for the next week. The campus interview/conversation was more discussional as opposed to being fired questions at. They were looking more to gauge past work-ex I think. For the on-site interview, I met with almost everyone in the team. It was a whole day process, starting in the morning and ending in the evening.
Confirmed questions2 questions
- Can you explain synthesis concepts, including the flow, different types of libraries, process corners, and some PD basics?
- Tell me about async. FIFO in verilog and provide relatively detailed conceptual questions.
SanDisk Silicon / Chip Design Engineer Interview Questions
Quoted word for word from SanDisk interview reports.
“For a NOR gate with inputs 0 and C, what would the output be?”
Read reports →“What are the effects of asynchronous reset signal assertion and deassertion on the system?”
Read reports →“Can you explain how a low pass RC filter circuit works?”
Read reports →“Can you explain the Ids/Vds characteristics of a MOSFET?”
Read reports →“What's the difference between a blocking and a non-blocking assignment?”
Read report →“Could you design a component that takes a 1-bit input with a pulse width of one clock cycle on `clk_in`, and outputs data on `clk_out` (which is faster/smaller)? The output should only be a single clock pulse on `clk_out`. What are the constraints on the rate for this component, considering only standard FPGA building blocks?”
Read report →“Can you explain the distinction between a function and a task in Verilog?”
Read report →“Could you explain the assertion and deassertion of an asynchronous reset signal and its system impact?”
Read report →“How would you go about detecting an overlapping sequence from an input stream?”
Read report →Formats, difficulty and experience
Across all 14 SanDisk interview reports.