Qualcomm Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 157 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Qualcomm.
Qualcomm
RTL Design Engineer
Senior Average Positive experience No offer 3 rounds
Interview process
Recruiter call Technical screen Panel Offer
Interview formats
Behavioral Technical
I applied in mid-October and had a technical screen in early December. Then, I was scheduled for a panel interview with 7 people in early January. After that, I was ghosted for almost 2 months, and now the website says I'm no longer being considered.
Confirmed questions3 questions
- Can you share your experience with writing testbenches, specifically regarding skew and other advanced features?
- What is your experience with Clock Domain Crossing (CDC) and First-In, First-Out (FIFO) buffers?
- Could you elaborate on your experience with the ASIC design flow?
Qualcomm
ASIC Verification Engineer
Entry Average Positive experience No offer 1 round
Interview process
Recruiter call Technical screen
Interview formats
Behavioral Technical Coding
The interview process was pretty smooth, and the interviewer was really friendly. We started with a quick chat about the role and my background, which took about 10 minutes. Then, they presented me with a case scenario and asked me to write a sequence_item for it.
Confirmed questions3 questions
- Can you explain cache coherence and its state diagram?
- What are your thoughts on the AXI protocol?
- Could you write a sequence_item for the input interface based on the scenario provided?
Qualcomm
Physical Design Engineer
Mid Difficult Negative experience No offer 2 rounds
Interview process
Recruiter call Phone screen
Interview formats
Technical Behavioral
You can apply through the Qualcomm careers website or via a referral. A recruiter might get in touch for an initial screening to discuss your background and the tools you've used, like ICC2, PrimeTime, RedHawk, etc. They'll want to know about your expertise in areas such as floorplanning, CTS, routing, STA, DRC, EMIR, and your experience with things like multi-VDD, ECOs, hierarchical designs, and colored flows. After that, there will be 1–2 technical phone interview rounds, each usually lasting about 45–60 minutes.
Confirmed questions5 questions
- Can you describe your process for floorplanning a block?
- How do you approach placing macros and standard cells around them?
- What factors do you take into account when designing a power grid?
Qualcomm Silicon / Chip Design Engineer Interview Questions
Quoted word for word from Qualcomm interview reports.
“What happens to the impedance of a resistor when it is in series with a MOSFET gate?”
Read reports →“What happens to the impedance of a resistor when it is in series with a MOSFET source (source degeneration)?”
Read reports →“Design the Verilog for a block that outputs '1' when the serial data pattern '0110' is detected, with synchronous clock input and output.”
Read reports →“If a FIFO operates with an input at 100MHZ and an output at 80MHZ, and 80 bits arrive every 100 cycles, what FIFO size is needed to prevent data loss?”
Read reports →“Create a bubble diagram for a Finite State Machine (FSM) solution to detect the serial pattern '0110'.”
Read report →“Using a simple logic gate, can you convert a SET type flop to a RESET type flop?”
Read report →“What is the FIFO depth for a design with 50W/100 cycles and 5R/10 cycles?”
Read report →“Can you write the verilog code for the Hamming (7,4) error detection and error correction?”
Read report →“Can you explain how to read a file in Unix and count a specific word using a single command script?”
Read report →Formats, difficulty and experience
Across all 157 Qualcomm interview reports.