NVIDIA Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 329 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at NVIDIA.
NVIDIA
ASIC Engineer
Mid Difficult Positive experience No offer 7 rounds
Interview process
Phone screen Technical screen Panel Onsite
Interview formats
Technical Coding System Design Behavioral Other
First Screening Round * 2 basic RTL questions, 1 scripting question * Blocking vs non blocking, reg vs wire * Python scripting question: file I/O, basic string parsing * 2nd RTL question: basic 2 stage adder, design Verilog module from given circuit description * Some resume questions Second Screening Round * More advanced scripting question on retiming registers * RTL question on accumulating data per address * Some theoretical FIFO questions (no coding) * Packed vs unpacked arrays discussed in depth Panel Round First Round * Simple scripting question on data conversion and string parsing (CSV) * Open-ended question about finding an error in a mux-based programmable delay circuit * Resume questions Second Round * Design a 10:1 mux using three 4:1 muxes * 80:20 to 8:2 module, questions on FIFO depth Third Round (Hiring Manager) * Fibonacci sequence in Python: iterative and recursive * Fibonacci sequence in Verilog: serial method, FSM design * Detailed talk about team functions, responsibilities, and day-to-day work Fourth Round * 4x4 multiplier in Verilog * Optimize to pipeline the multiplies * Optimize to use a single MAC unit and feed data serially * Second largest sum in a Python list Fifth Round * Debugging a Perl script * Many questions about intermediate expressions in Verilog and possible data-loss
Confirmed questions1 question
- First Screening Round * 2 basic RTL questions, 1 scripting question * Blocking vs non blocking, reg vs wire * Python scripting question: file I/O, simple string parsing * Second RTL question: basic 2 stage adder, write Verilog module from circuit description * Some resume-based questions Second Screening Round * More advanced scripting question focused on retiming registers * RTL question about accumulating data for each address * A few theoretical FIFO questions (no actual coding) * In-depth discussion on packed vs unpacked arrays Panel Round First Round * Basic scripting task on data conversion and CSV string parsing * Open-ended problem to locate an error in a mux-based programmable delay circuit * Resume-related questions Second Round * Design a 10:1 mux built from three 4:1 muxes * 80:20 to 8:2 module question, including FIFO depth Third Round (Hiring Manager) * Fibonacci sequence in Python: both iterative and recursive versions * Fibonacci sequence in Verilog: serial implementation, FSM-based design * Detailed discussion on team roles, responsibilities, and daily work Fourth Round * Implement a 4x4 multiplier in Verilog * Improve it by pipelining the multiplies * Further optimize using a single MAC unit with serial data input * Find the second largest sum in a Python list Fifth Round * Debug a Perl script * Many questions on intermediate Verilog expressions and potential data loss
NVIDIA
ASIC Design Engineer
Intern Average Neutral experience No offer 2 rounds
Interview process
Technical screen
Interview formats
Technical Coding
Two 45-minute interviews happened back-to-back with no break. One was a technical session and the other was a coding session (Verilog or SystemVerilog). I got rejected after around two days, but I was still allowed to interview with other teams.
Confirmed questions2 questions
- The first interview had basic technical questions on logic design, STA, FSM etc.
- The second interview was RTL coding for a synchronous FIFO with depth=5.
NVIDIA
ASIC Design Engineer
Entry Easy Neutral experience No offer 1 round About 2 weeks
Interview process
Recruiter call Technical screen
Interview formats
Behavioral Technical
Applied Online >> got a Recruiter Email >> had an Online Interview assigned. Just a quick note — the interviewer ended up being different than the one originally mentioned, and I wasn’t told about the change. Also, the HackerRank link that was included didn’t really seem needed. Not a big deal, and it wouldn’t have changed anything, just thought I’d mention it.
Confirmed questions7 questions
- Started with Introduce Yourself.
- Resume Question: You talk about the Boot and Fuse Controller in your project. Explain that to me.
- More questions on why the Fuse is important in an SoC.
NVIDIA Silicon / Chip Design Engineer Interview Questions
Quoted word for word from NVIDIA interview reports.
“is there any benefit to using a cache if there is a read miss for every single access?”
Read reports →“12V source in series with 3 caps with given capacitances, the last one tied to gnd. If the node between the first and second cap starts open and then is closed, what are the resulting node voltages?”
Read reports →“there are 1000 wires where any number of them can be swapped among each other. how many different bit patterns would you apply at the input side to find the correct set of wires that are swapped?”
Read reports →“Given a MxN matrix of 0's and 1's, whenever you hit a cell with value 1, you need to change all cells in its row and column to 0's.”
Read reports →“If we have balls numbered from one to n and one ball is randomly taken out, how can we figure out which ball is missing with O(1) memory complexity?”
Read report →“Is it possible to do write and read from a sync FIFO made using single port sram in the same clock cycle?”
Read report →“Clock skew? Is it good or bad for a circuit with 2 flops and combinational logic in between.”
Read report →“3) Flip flop A -> Flip flop B -> Flip flop C - output of flip flop C is fed back to flip flop A. Combinational delay between A and B is 3ns, between B and C is 4ns, between C and A is 5ns. Case a) Find max operating freq? [setup = 1ns, hold = 1ns, clock to q =0] Case b) Now make flip flop B neg edge triggered. Find max operating freq?”
Read report →“5. in a given circuit, to meet timing how many retiming flops should be inserted? (based on setup analysis)”
Read report →Formats, difficulty and experience
Across all 329 NVIDIA interview reports.