Juniper Networks Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 24 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Juniper Networks.
Juniper Networks
ASIC Design Verification Engineer
Mid Easy Positive experience No offer 3 rounds
Interview process
Recruiter call Technical screen Onsite
Interview formats
Technical Coding Behavioral
The interviewer started with some basic questions and then moved on to more complex ones. They asked about SV assertions, fork join, swap, and recursive functions for Fibonacci series. It's important to prepare your resume thoroughly. They also asked me to describe my experience in detail.
Confirmed questions4 questions
- Can you explain System Verilog and C-based questions?
- What is fork join?
- Tell me about assertions.
Juniper Networks
ASIC Engineer
Mid Average Positive experience No offer 6 rounds
Interview process
Phone screen Onsite
Interview formats
Technical Coding System Design
So there was one phone interview where they asked me about my projects and then one easy design question. After that, I had an on-site interview the following week. It was a 5 round interview in total. They asked me problems about timing issues, setup, and hold time violations, and pattern detection. I also had to write some Verilog code and they asked about SRAM, DDR, and how to design a TCAM.
Confirmed questions8 questions
- Regarding an inverter with its input connected to its output, what would its output voltage curve resemble?
- Could you describe your projects?
- What is your approach to a simple design problem?
Juniper Networks
ASIC Design Engineer
Mid Difficult Neutral experience No offer 1 round
Interview process
Recruiter call Technical screen Onsite
Interview formats
Behavioral Technical Other
The interview had several parts. Some interviewers wanted to hear about my past work at other companies. Others asked questions that required unconventional thinking, and there was one session focused on a problem not directly related to ASIC design, which was meant to gauge my thought process. The whole thing lasted about 4-5 hours straight, no lunch break, so I was pretty drained by the end.
Confirmed questions1 question
- Can you tell me about the most difficult design problem you've faced and how you solved it?
Juniper Networks Silicon / Chip Design Engineer Interview Questions
Quoted word for word from Juniper Networks interview reports.
“What is the outcome of connecting the output of a NAND gate to its input?”
Read reports →“Regarding an inverter with its input connected to its output, what would its output voltage curve resemble?”
Read reports →“Problem: In a group of 30 people at a party, what's the probability that no two share the same birthday?”
Read reports →“Can you explain why gray code is used in sampling instead of binary?”
Read reports →“Regarding FIFO depth: If a writer produces 6 locations in 10 units and a reader consumes 60 locations in 100 units, and both operate continuously once started, what is the required buffer depth?”
Read report →“What are setup and hold times, and what is their purpose?”
Read report →“How do you implement latches and flops in Verilog?”
Read report →“Can you explain how to decrease the DDR2 access time?”
Read report →“Can you explain how to set up a hold when the output of the second flip-flop is used as the input of the first flip-flop?”
Read report →Formats, difficulty and experience
Across all 24 Juniper Networks interview reports.