Hudson River Trading Hardware Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 5 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Hudson River Trading.
Hudson River Trading
Hardware Design Engineer
Entry Difficult Neutral experience No offer 2 rounds
Interview process
Technical screen Take home
Interview formats
Technical Coding
I had one zoom interview that was about 40 minutes long with rapid technical questions. They didn't give feedback when I was wrong, but they would ask more in-depth questions when I was right. The second round was a take-home assignment where I had to write verilog code to pass a given testbench.
Confirmed questions0 questions
No confirmed questions were included in this interview report.
Hudson River Trading
Hardware Engineer Intern
Intern Average Positive experience Decline offer 2 rounds
Interview process
Technical screen Take home
Interview formats
Technical Coding
I was given a systemverilog programming task, then had some online technical interviews about FPGAs and how they work. They even sent me free headphones.
Confirmed questions2 questions
- Can you describe the synthesis stage in FPGA design?
- What about the implementation stage?
Hudson River Trading
Hardware Engineer
Intern Average Negative experience No offer 3 rounds
Interview process
Take home Phone screen Technical screen
Interview formats
Coding Technical
The interview process includes a take-home test where you need to design and verify a system in Verilog. If you pass that, there's a phone screen asking about FPGA components, OS, memory management, pointers, verification, and paging. Passing that leads to a live coding interview, which is a simple Python test, not meant to be super hard.
Confirmed questions4 questions
- Can you discuss pointers?
- Tell me about memory management.
- What is garbage collection?
Hudson River Trading Hardware Engineer Interview Questions
Quoted word for word from Hudson River Trading interview reports.
“Design a two-stage pipelined ALU for handling hex instructions.”
Read reports →“What is garbage collection?”
Read reports →“Can you describe the synthesis stage in FPGA design?”
Read reports →“Could you explain setup and hold time violations and how to fix them?”
Read reports →“Do you know about LUTs?”
Read report →“What about the implementation stage?”
Read report →“Can you discuss pointers?”
Read report →“Tell me about memory management.”
Read report →Formats, difficulty and experience
Across all 5 Hudson River Trading interview reports.