Cadence Design Systems Silicon / Chip Design Engineer Interview Questions
& Process
Real candidates share what happened, how many rounds they had,
and how the experience turned out.
Based on 21 interview experiences · FREE TO READ
Candidate interview experiences
First-hand accounts from people who interviewed at Cadence Design Systems.
Cadence Design Systems
Analog IC Design Engineer
Mid Average Positive experience Accept offer 3 rounds
Interview process
Technical screen Technical screen Recruiter call
Interview formats
Technical Technical Behavioral
There were two technical rounds and then an HR round. The first technical round involved questions about the gain of simple topologies like a MOSFET with a current source and source resistance, asking for gain at the source and drain when input is applied at the gate. It also covered current mirror accuracy and CMOS inverters. The second technical round focused on OTAs, specifically how to reduce PSRR in a given topology, and the setup time of digital circuits.
Confirmed questions4 questions
- Regarding PSRR for a diff amp with an active load pmos, how do you reduce it?
- How can the accuracy of a current mirror be made 100%?
- If the mirror node in an OTA had infinite capacitance, what would happen to the gain and output impedance?
Cadence Design Systems
IC Design Engineer
Entry Difficult Positive experience Accept offer 3 rounds
Interview process
Recruiter call Onsite Offer
Interview formats
Behavioral Technical
I found this junior Design Engineer job online and applied. A couple weeks later, the Design Engineering Director emailed me for a phone interview. It was non-technical and went for about 30-60 minutes. After that, the director asked me to come in for an on-site interview in Columbia, MD. This on-site was technical and took around 5 hours. The next day, the director called again and said they were gonna make me an offer.
Confirmed questions5 questions
- Tell me about your understanding of ADCs.
- Can you explain bandgap references?
- What do you know about noise in electronic systems?
Cadence Design Systems
Physical Design Engineer
Lead Average Negative experience No offer 2 rounds
Interview process
Recruiter call Technical screen
Interview formats
Technical Behavioral
I applied through LinkedIn for a Pune based role. A recruiter scheduled an interview. We had 4 rounds scheduled, but only ended up doing 2 rounds, each about 45 minutes long. After the interviews, it's been over a week with no word from HR about whether I've been shortlisted. It feels like there's a lack of transparency in this process.
Confirmed questions8 questions
- Can you describe what IR is?
- Could you explain EM?
- What is latency in your understanding?
Cadence Design Systems Silicon / Chip Design Engineer Interview Questions
Quoted word for word from Cadence Design Systems interview reports.
“If the mirror node in an OTA had infinite capacitance, what would happen to the gain and output impedance?”
Read reports →“How do RC circuits behave before voltage is applied?”
Read reports →“How do RC circuits behave after voltage is applied?”
Read reports →“How can the accuracy of a current mirror be made 100%?”
Read reports →“Regarding PSRR for a diff amp with an active load pmos, how do you reduce it?”
Read report →“How do you approach input resistances in feedback systems?”
Read report →“Can you implement a logic circuit that introduces a one-clock delay?”
Read report →“What is the function of the Cadence Encounter tool?”
Read report →“Based on the sum, how do you calculate setup and hold times?”
Read report →Formats, difficulty and experience
Across all 21 Cadence Design Systems interview reports.