Altera Silicon / Chip Design Engineer interviews, decoded.

This involved multiple 30-minute sessions spread across two rounds. The interviews were mostly technical, with minimal focus on soft skills or personal background. The content covered both software and hardware aspects.

Had a phone interview for about 45 minutes, then there were 3 more interviews that were onsite. The first onsite was pretty long, 2.5 hours. The second one was shorter, just 1 hour. The third onsite interview was 1.5 hours long. The initial phone interview was about my knowledge of uvm, system verilog, and C++. During the first onsite, I met 3 people and we talked about my projects, UVM, system verilog, and C++. In the second interview, I met one person who mainly asked about my past verification projects, assertions, and functional coverage. For the third onsite, I met 2 people and they focused on UVM and system verilog questions.

The work is mainly about design and verification engineer on block-level and subsystem-level verification, with possible exposure to some design and synthesis work too. The interview focused on my academic projects, which included designing a 5-stage MIPS processor, a DMA controller, and a high-performance multiplier.